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MPC2105A ? mpc2106a ? mpc2105b ? mpc2106b 1 motorola fast sram 512kb and 1mb burstram ? secondary cache modules for powerpc ? prep/chrp platforms the MPC2105A/b and the mpc2106a/b are designed to provide burstable, high performance l2 cache for the powerpc 60x microprocessor family in conformance with the powerpc reference platform (prep) and the powerpc common hardware reference platform (chrp) specifications. the MPC2105A/b and mpc2106a/b utilize synchronous burstrams. the modules are configured as 64k x 72, and 128k x 72 bits in a 178 (89 x 2) pin dimm format. the MPC2105A/b uses four of the 3 v 64k x 18; the mpc2106a/b uses eight of the 3 v 64k x 18. for tag bits, a 5 v cache tag ram c onfigured as 16k x 12 for tag field plus 16k x 2 for valid and dirty status bits is used. bursts can be initiated with the ads signal. subsequent burst addresses are generated internal to the burstram by the cnten signal. write cycles are internally self timed and are initiated by the rising edge of the clock (clkx) inputs. eight write enables are provided for byte write control. presence detect pins are available for auto configuration of the cache control. the module family pinout will support 5 v and 3.3 v components for a clear path to lower voltage and power savings. both power supplies must be connected. all of these cache modules are plug and pin compatible with each other. ? powerpcstyle burst counter on chip ? flowthrough data i/o ? plug and pin compatibility ? multiple clock pins for reduced loading ? 20 w series resistors on dl and dh pins for noise reduction (MPC2105A/6a) ? all cache data and tag i/os are lvttl (3.3 v) compatible ? three state outputs ? byte write capability ? fast module clock rates: up to 66 mhz ? fast sram access times: 10 ns for tag ram match 9 ns for data ram ? decoupling capacitors for each fast static ram ? high quality multilayer fr4 pwb with separate power and ground planes ? 178 pin card edge module ? burndy connector, part number: elf178ksc3z50 burstram is a trademark of motorola. the powerpc name is a trademark of ibm corp., used under license therefrom. order this document by MPC2105A/d semiconductor technical data MPC2105A mpc2106a mpc2105b mpc2106b 178lead card edge top view MPC2105A/b case 1132a01 mpc2106a/b case 113201 80 25 24 1 48 47 rev 1 12/19/96 ? motorola, inc. 1996
MPC2105A ? mpc2106a ? mpc2105b ? mpc2106b 2 motorola fast sram MPC2105A/b block diagram a0 = nc clk3 = nc clk4 = nc ale = nc ads1 = nc cnten1 = nc cg1 = nc addr0 = nc addr1 = nc dh24 dh31 + dp3 clk1 dl16 dl23 + dp6 dl24 dl31 + dp7 note: ba28 is tied to sa0 on sram; ba27 is tied to sa1 on sram; standby is tied to se3 on sram. 69f618atq g se1 adsc cg0 sa adv ads0 cwe1 clk0 dh0 dh7 + dp0 dh8 dh15 + dp1 cwe0 cnten0 cwe2 clk0 dh16 dh23 + dp2 cwe3 k dqb dqa cwe4 sbb sba clk1 dl0 dl7 + dp4 dl8 dl15 + dp5 cwe5 cwe6 cwe7 v ss k dqb dqa sbb sba k dqb dqa sbb sba k dqb dqa sbb sba 69f618atq 69f618atq 69f618atq g se1 adsc sa adv g se1 adsc sa adv g se1 adsc sa adv '244 a13 a28 ba13 ba28 pd3 pd2 pd1 pd0 j2 j0 j3 a13 a26 a1 a12 tclr twe clk2 match validin dirtyin tg tag: 16k x 12 + v + d a0 a13 reset tag0 11 tah, tag , tad sfunc, sg sw tw k validd dirtyd tg tt1, wtd, e1 e2, pwrdn v ss v cc via 100 w wtq ta , validq v ccq v dd nc match dirtyout dirtyq se2 sgw adsp sw zz sram tie off j1 v cc v cc v dd
MPC2105A ? mpc2106a ? mpc2105b ? mpc2106b 3 motorola fast sram mpc2106a/b block diagram a13 a26 a0 a11 tclr twe clk2 match validin dirtyin tg tag: 16k x 12 + v + d a0 a13 reset tag0 11 tah, tag , tad sfunc, sg sw tw k e2 validd dirtyd tg ale = nc addr0 = nc addr1 = nc dh24 dh31 + dp3 clk4 dl16 dl23 + dp6 dl24 dl31 + dp7 tt1, wtd pwrdn v ss v cc via 100 w wtq ta , validq v ccq v dd nc a12 69f618atq g se1 adsc cg0 sa adv ads0 cwe0 clk0 dh0 dh7 + dp0 dh8 dh15 + dp1 cwe1 cnten0 cwe2 clk1 dh16 dh23 + dp2 cwe3 k dqb dqa cwe4 sbb sba clk3 dl0 dl7 + dp4 dl8 dl15 + dp5 cwe5 cwe6 cwe7 k dqb dqa sbb sba k dqb dqa sbb sba k dqb dqa sbb sba 69f618atq 69f618atq 69f618atq g se1 adsc sa adv g se1 adsc sa adv g se1 adsc sa adv '244 a13 a28 ba13 ba28 pd3 pd2 pd1 pd0 j2 j0 j3 j1 69f618atq g se2 adsc cg1 sa adv ads1 cnten1 k dqa dqb sba sbb k dqa dqb sba sbb k dqa dqb sba sbb k dqa dqb sba sbb 69f618atq 69f618atq 69f618atq g se2 adsc sa adv g se2 adsc sa adv g se2 adsc sa adv a12 ba12 bank a: se2 tied to. v dd via 100 w. bank b: se1 tied to. v ss match dirtyout dirtyq e1 v cc e2 a12 e1 v ss note: ba28 is tied to sa0 on sram; ba27 is tied to sa1 on sram; standby is tied to se3 on sram. sgw adsp sw zz sram tie off v dd v cc v cc
MPC2105A ? mpc2106a ? mpc2105b ? mpc2106b 4 motorola fast sram pin assignment 178lead dimm pin name pin name pin name pin name pin name pin name pin name 1 v ss 27 dh0 53 dl1 79 v ss 105 dh14 131 dl17 157 a22 2 pd0/idsclk 28 dp0 54 dl0 80 a7 106 dh13 132 cwe6 158 a20 3 pd2 29 v ss 55 v ss 81 a5 107 v cc 133 dl15 159 v ss 4 dh30 30 clk1 56 clk2 82 a3 108 dh10 134 dl13 160 a18 5 dh28 31 v ss 57 v ss 83 a0 109 dh8 135 v ss 161 a16 6 dh26 32 dl28 58 dp4 84 v cc 110 cwe1 136 dl10 162 a15 7 dh24 33 dl26 59 cg0 85 tclr 111 dh6 137 dl8 163 a14 8 v dd 34 dl24 60 cg1 86 match 112 v dd 138 cwe5 164 v dd 9 dp3 35 dp7 61 v dd 87 tg 113 dh4 139 dl6 165 a10 10 dh22 36 v cc 62 addr0 88 dirtyin 114 v ss 140 v dd 166 a8 11 dh20 37 dl22 63 reserved 89 v ss 115 clk0 141 dl5 167 a6 12 dh19 38 dl20 64 ads0 90 v ss 116 v ss 142 dl2 168 v ss 13 v ss 39 dl18 65 ads1 91 pd1/idsdata 117 dh1 143 v ss 169 a4 14 dh17 40 dl16 66 a28 92 pd3 118 cwe0 144 clk3 170 a2 15 dp2 41 v ss 67 a26 93 dh31 119 dl31 145 v ss 171 a1 16 dh15 42 dp6 68 a25 94 dh29 120 dl30 146 clk4 172 burstmode 17 dh12 43 dl14 69 a23 95 dh27 121 v ss 147 v ss 173 v cc 18 v cc 44 dl12 70 v ss 96 dh25 122 dl29 148 cwe4 174 validin 19 dh11 45 dl11 71 a21 97 v dd 123 dl27 149 ale 175 twe 20 dh9 46 v ss 72 a19 98 cwe3 124 dl25 150 v dd 176 standby 21 dp1 47 dl9 73 a17 99 dh23 125 v cc 151 addr1 177 dirtyout 22 dh7 48 dp5 74 a13 100 dh21 126 cwe7 152 reserved 178 v ss 23 v dd 49 dl7 75 v dd 101 dh18 127 dl23 153 cnten0 24 dh5 50 dl4 76 a12 102 v ss 128 dl21 154 cnten1 25 dh3 51 v dd 77 a11 103 dh16 129 dl19 155 a27 26 dh2 52 dl3 78 a9 104 cwe2 130 v ss 156 a24 note: v cc and v dd must be connected on all modules. top view 1 24 25 89 90 113 114 178 47 136 48 137
MPC2105A ? mpc2106a ? mpc2105b ? mpc2106b 5 motorola fast sram pin descriptions pin locations symbol type description 66, 67, 68, 69, 71, 72, 73, 74, 76, 77, 78, 80, 81, 82, 83, 155, 156, 157, 158, 160, 161, 162, 163, 165, 166, 167, 169, 170, 171 a0 a28 input address inputs (msb:0, lsb:28). 62 addr0 input least significant address bit when asynchronous data rams are used. 151 addr1 input next to least significant address bit when asynchronous data rams are used. 64, 65 ads0 , ads1 input data ram address strobe for MPC2105A/b use ads0 only. for mpc2106a/b use ads0 , ads1 . 149 ale input data ram address latch enable use for asynchronous data ram only. 172 burstmode input burstmode. 0 = linear, 1 = interleaved. 59, 60 cg0 , cg1 input data ram output enables for MPC2105A/b use cg0 only. for mpc2106a/b use cg0 , cg1 . 30, 56, 115, 144, 146 clk0 clk4 input clock inputs clk2 is for tag ram, clk0, 1, 3, and 4 are for data rams only. for mpc2106a/b use all the clocks. for MPC2105A/b use clk0 clk2 only. 153, 154 cnten0 , cnten1 input data ram count enables for MPC2105A/b use cnten0 only. for mpc2106a/b use cnten0 , cnten1 . 98, 104, 110, 118, 126, 132, 138, 148 cwe0 cwe7 input data ram write enables (msb:0, lsb:7). 4, 5, 6, 7, 10, 11, 12, 14, 16, 17, 19, 20, 22, 24, 25, 26, 27, 93, 94, 95, 96, 99, 100, 101, 103, 105, 106, 108, 109, 111, 113, 117 dh0 dh31 i/o high data bus (msb:0, lsb:31). 88 dirtyin input dirty input bit. 177 dirtyout output dirty output bit. 32, 33, 34, 37, 38, 39, 40, 43, 44, 45, 47, 49, 50, 52, 53, 54, 119, 120, 122, 123, 124, 127, 128, 129, 131, 133, 134, 136, 137, 139, 141, 142 dl0 dl31 i/o low data bus (msb:0, lsb:31). 9, 15, 21, 28, 35, 42, 48, 58 dp0 dp7 i/o data parity bits (msb:0, lsb:7) 86 match output tag ram active high match indication. 2 pd0/idsclk input presence detect bit 0/eeprom serial clock. (eeprom option only). 91 pd1/idsdata i/o presence detect bit 1/eeprom serial data. (eeprom option only). 3, 92 pd2, pd3 output presence detect bits. 63, 152 reserved reserved pin. 176 standby input standby pin. reduces standby power consumption. 85 tclr input tag ram clear. 87 tg input tag ram output enable. 175 twe input tag ram write enable. 174 validin input tag ram valid bit. 18, 36, 84, 107, 125, 173 v cc input + 5 v power supply. must be connected. 8, 23, 51, 61, 75, 97, 112, 140, 150, 164 v dd input + 3.3 v power supply. must be connected. 1, 13, 29, 31, 41, 46, 55, 57, 70, 79, 89, 90, 102, 114, 116, 121, 130, 135, 143, 145, 147, 159, 168, 178 v ss input ground.
MPC2105A ? mpc2106a ? mpc2105b ? mpc2106b 6 motorola fast sram data ram mcm69f618a synchronous truth table (see notes 1, 2, and 3) standby adsx cntenx cwex clkx address used operation h l x x lh n/a deselected l l x l lh external address write cycle, begin burst l l x h lh external address read cycle, begin burst x h l l lh next address write cycle, continue burst x h l h lh next address read cycle, continue burst x h h l lh current address write cycle, suspend burst x h h h lh current address read cycle, suspend burst notes: 1. x means don't care. 2. all inputs except cg must meet setup and hold times for the lowtohigh transition of clock (clk0 clk4). 3. wait states are inserted by suspending burst. asynchronous truth table (see notes 1 and 2) operation cg i/o status read l data out (dq0 dq8) read h highz write x highz e data in deselected x highz notes: 1. x means don't care. 2. for a write operation following a read operation, cg must be high before the input data required setup time and held high through the input data hold time. absolute maximum ratings (voltages referenced to v ss = 0 v) rating symbol value unit power supply voltage v cc 0.5 to + 7.0 v voltage relative to v ss v in , v out 0.5 to v cc + 0.5 v output current (per i/o) data ram ta g i out 30 20 ma power dissipation MPC2105A/b mpc2106a/b p d 4.6 9.2 w temperature under bias t bias 10 to + 85 c operating temperature t a 0 to +70 c storage temperature t stg 55 to + 125 c note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended oper- ating conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. this device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maxi- mum rated voltages to this highimpedance circuit. this bicmos memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. this device contains circuitry that will ensure the output devices are in highz at power up.
MPC2105A ? mpc2106a ? mpc2105b ? mpc2106b 7 motorola fast sram dc operating conditions and characteristics (v cc = 5.0 v 5%, v dd = 3.3 v 10%, t a = 0 to + 70 c, unless otherwise noted) recommended operating conditions (voltages referenced to v ss = 0 v) parameter symbol min max unit supply voltage (operating voltage range) v cc v dd 4.75 3.00 5.25 3.60 v input high voltage v ih 2.2 v dd + 0.3** v input low voltage v il 0.5* 0.8 v *v il (min) = 0.5 v dc; v il (min) = 2.0 v ac (pulse width 20 ns) for i 20.0 ma. ** v ih (max) = v dd + 0.3 v dc; v ih (max) = v dd + 2.0 v ac (pulse width 20 ns) for i 20.0 ma. dc characteristics parameter symbol min max unit input leakage current (all inputs, v in = 0 to v dd ) data ram ta g i lkg(i) e 1.0 5.0 m a output leakage current (cg = v ih , v out = 0 to v dd ) data ram ta g i lkg(o) e 1.0 5.0 m a ttl output low voltage (i ol = + 8.0 ma) v ol e 0.4 v ttl output high voltage (i oh = 4.0 ma) v oh 2.4 e v power supply currents parameter symbol max unit ac supply current (cg = v ih , e = v il , i out = 0 ma, all inputs = v il and v ih , v il = 0.0 v and v ih 3.0 v, cycle time 20 ns) MPC2105A/b mpc2106a/b i dda 900 1800 ma MPC2105A/b mpc2106a/b i cca 320 640 ma ac standby current (e = v ih , i out = 0 ma, all inputs = v il or v ih v il = 0.0 v and v ih 3.0 v, cycle time 20 ns) MPC2105A/b mpc2106a/b i sb1 (v dd ) 440 880 ma MPC2105A/b mpc2106a/b i sb1 (v cc ) 320 640 ma capacitance (f = 1.0 mhz, dv = 3.0 v, t a = 25 c, periodically sampled rather than 100% tested) parameter symbol typ max unit input capacitance (a13 a28) (data ram control pins) (clk0 clk4) (tag control pins) c in e 16 8 e 15 20 10 5 pf tag output capacitance (match, dirtyout) c out e 7 pf data ram input/output capacitance (dh0 dh31, dl0 dl31) c i/o 6 8 pf tag input/output capacitance (a0 a11) c i/o e 7 pf
MPC2105A ? mpc2106a ? mpc2105b ? mpc2106b 8 motorola fast sram data rams ac operating conditions and characteristics (v cc = 5.0 v 5%, v dd = 3.3 v 10% t a = 0 to + 70 c, unless otherwise noted) input timing measurement reference level 1.5 v . . . . . . . . . . . . . . . input pulse levels 0 to 3.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall time 3 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output timing reference level 1.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . output load see figure 1a unless otherwise noted . . . . . . . . . . . . . synchronous data rams read/write cycle timing (see notes 1, 2, and 3) MPC2105A/b mpc2106a/b parameter symbol min max unit notes cycle time t khkh 15 e ns clock access time t khqv e 9 ns 4 output enable to output valid t glqv e 5 ns clock high to output active t khqx1 6 e ns clock high to output change t khqx2 3 e ns output enable to output active t glqx 0 e ns output disable to q highz t ghqz 2 6 ns clock high to q highz t khqz e 6 ns clock high pulse width t khkl 5 e ns clock low pulse width t klkh 5 e ns setup time address t avkh 7.5 e ns 5, 6 setup times: address status data in write address advance chip enable t svkh t dvkh t wvkh t bavvkh t evkh 2.5 e ns 5 hold times: address address status data in write address advance chip enable t khax t khtsx t khdx t khwx t khbax t khex 0.5 e ns 5 notes: 1. in setup and hold times, w (write) refers to either one or both byte write enables lw and uw . 2. all read and write cycle timings are referenced from clk or cg . 3. cg is a don't care when uw or lw is sampled low. 4. maximum access times are guaranteed for all possible powerpc external bus cycles. 5. this is a synchronous device. all addresses must meet the specified setup and hold times for all rising edges of clk whenever tsp or tsc is low, and the chip is selected. all other synchronous inputs must meet the specified setup and hold times for all rising edges of clk when the chip is enabled. chip enable must be valid at each rising edge of clock for the device (when tsp or tsc is low) to remain enabled. 6. 5 ns of setup delay is incurred in address buffers.
MPC2105A ? mpc2106a ? mpc2105b ? mpc2106b 9 motorola fast sram synchronous data ram read cycle clk1, clk0 ads0 a(12, 13 26) (see note 1) cwe0 cwe7 standby cnten0 cg data out read burst read t khkh t khkl t klkh a1 a2 t avkh t khax t khqx1 t ghqz t khqv t khqz q (a1) q (a2) q (a2 + 1) q (a2 + 2) t tsvkh t khtsx t wvkh t khwx t evkh t khex t bavkh t khbax t khqv t glqv t glqx t khqx2 notes: 1. cache addresses used are: 13 26 for MPC2105A/b; and 12 26 for mpc2106a/b. 2. q1 (a2) represents the first ouput from the external address a2; q2 (a2) represents the next output data in the burst sequence with a2 as the base address. q (a2 + 3)
MPC2105A ? mpc2106a ? mpc2105b ? mpc2106b 10 motorola fast sram synchronous data ram write cycle clk1, clk0 ads0 a(12, 13 26) cwe0 cwe7 standby cnten0 data in single write burst write t khkh t khkl t klkh a1 a2 t avkh t khax d (a1) d (a2) d (a2 + 1) d (a2 + 2) t wvkh t khwx t evkh t khex t bavkh t khbax notes: 1. cache addresses used are: 13 26 for MPC2105A/b; and 12 26 for mpc2106a/b. 2. cg0 = v ih t svkh t khtsx t avkh t khax d (a2 + 3) t dvkh t khdx
MPC2105A ? mpc2106a ? mpc2105b ? mpc2106b 11 motorola fast sram tag ram reset function truth table (see notes 1 and 2) tclr clk twe tag0 tag11 dirtyout match operation power l l h h highz l (3) l (3) reset status active l l h l e e e not allowed e notes: 1. h = v ih , l = v il , x = don`t care, e = undefined. 2. tg is x for this table. 3. these are output states. read function truth table (see notes 1, 2, and 3) tg twe clk tag0 tag11 validin dirtyin dirtyout match operation l h x d out e e d out d out read tag i/o h x x highz e e e e tag i/o disable write function truth table (see notes 1 and 2) tg twe clk tag0 tag11 validin dirtyin dirtyout match operation h l l h d in e e e l write tag i/o l l l h e e e e e not allowed notes: 1. h = v ih , l = v il , x = don`t care, e = undefined. 2. this table applies when reset and pwrdn are high. 3. d out in this case is the same as d in . the input data is written through to the outputs during the write operation. match function truth table (see notes 1 through 4) tg twe tag0 tag11 validin (4) dirtyin (4) match operation x x e e e d out selected l h d out e e l read tag i/o h l d in d in d in l write tag i/o, status bits h h tag in l e l invalid data dedicated status bits h h tag in h e h match dedicated status bits notes: 1. h = v ih , l = v il , x = don`t care, e = undefined. 2. m = high if tag in equals the memory contents at the address; m = low if tag in does not equal the contents at that address. 3. pwrdn and reset are high for this table. gs and clk are x. 4. this column represents the stored memory cell data for the given status bit at the selected address.
MPC2105A ? mpc2106a ? mpc2105b ? mpc2106b 12 motorola fast sram tag ram ac operating conditions and characteristics (v cc = 5.0 v 5%, t a = 0 to + 70 c, unless otherwise noted) input timing measurement reference level 1.5 v . . . . . . . . . . . . . . . input pulse levels 0 to 3.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall time 3 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output timing measurement reference level 1.5 v . . . . . . . . . . . . . output load figure 1a unless otherwise noted . . . . . . . . . . . . . . . . . tag ram read cycle (see notes 1 through 4) tag ram parameter symbol min max unit clock access time t khqv e 10 ns output enable to output valid t glqv e 8 ns output enable to output active t glqx 0 e ns output disable to q highz t ghqz 1 6 ns status bit hold from address change t axsx 3 e ns address access time status bits t avsv e 10 ns tag bit hold from address change t avqx 3 e ns address access time tag bits t avqv e 12 ns notes: 1. setup and hold times, w (write) refers to twe . 2. a read cycle is defined by twe high. a write cycle is defined by twe low. 3. maximum access times are guaranteed for all possible mc68040 and powerpc external bus cycles. 4. tag reads are asynchronous. tag ram write cycle (see notes 1 through 4) tag ram parameter symbol min max unit cycle time t khkh 15 e ns clock high pulse width t khkl 4.5 e ns clock low pulse width t klkh 4.5 e ns clock high to output active t khqx 1.5 e ns setup times address write t avkh t wvkh 3 e ns hold times address write t khax t khwx 1.5 e ns status output hold t khsx 0 e ns clock high to status bits valid t khsv e 9 ns notes: 1. setup and hold times, w (write) refers to twe . 2. a read cycle is defined by twe high. a write cycle is defined by twe low. 3. maximum access times are guaranteed for all possible mc68040 and powerpc external bus cycles. 4. tag writes are synchronous.
MPC2105A ? mpc2106a ? mpc2105b ? mpc2106b 13 motorola fast sram tag ram write and read cycles clk a(12, 13,26 twe a0 a11 tg valid valid valid valid input valid output valid output valid output valid valid valid valid valid t avkh t khax status write tag read tag write after read t wvkh t khwx t wvkh t khwx t khsv t khsx t wvkh t khwx t khqv t khqx t avsv t ghqz t glqx t axsx validin dirtyin dirtyout t khkl t klkh t khkh t glqv (see note 2) (see note 3) t avqv t axqx t avkh t khax (see note 1) (see note 1) t avsv t axsx notes: 1. transition is measured plus or minus 200 mv from steady state. 2. tclr = high. tag read after write 3. cache addresses used are: a13 26 for MPC2105A, a12 26 for mpc2106a.
MPC2105A ? mpc2106a ? mpc2105b ? mpc2106b 14 motorola fast sram tag ram match cycle tag ram parameter symbol min max unit clock high write to match invalid t khml e 7 ns clock high read to match valid t khmv e 10 ns address valid to match valid t avmv e 10 ns match valid hold from address change t axmx 2 e ns tg low to match invalid t glml e 7 ns tg high to match valid t ghmx e 8 ns tag ram reset (tclr ) cycle tag ram parameter symbol min max unit tclr setup time t stc 4 e ns tclr hold time t htc 1 e ns status bit reset time t srst e 60 ns status bit hold from tclr low t shrs 2 e ns tclr low to match invalid t rsml e 10 ns tclr high to match valid t rsmv e 100 ns tclr low to tag highz t rsqz e 10 ns tclr high to tag active t rsqx e 100 ns standby setup to tclr low t pdsr 30 e ns tclr high to twe low t rhwx 80 e ns output z 0 = 50 w 50 w v l = 1.5 v (a) (b) 5 pf +5 v output 255 w 480 w timing limits the table of timing values shows either a minimum or a maximum limit for each param- eter. input requirements are specified from the external system point of view. thus, ad- dress setup time is shown as a minimum since the system must supply at least that much time. on the other hand, responses from the memory are specified from the de- vice point of view. thus, the access time is shown as a maximum since the device never provides data later than that time. figure 1. test loads
MPC2105A ? mpc2106a ? mpc2105b ? mpc2106b 15 motorola fast sram match clk a(12, 13 26* tag ram match cycle valid match valid valid t avmv t axmx t khwx t khwx t wvkh t wvkh t wvkh twe a0 a11 tg valid address valid match data from: processor processor tag ram valid t glml t glmx t khml t khmv * cache addresses used are: a13 26 for MPC2105A, a12 26 for mpc2106a.
MPC2105A ? mpc2106a ? mpc2105b ? mpc2106b 16 motorola fast sram match clk t htc tag ram tclr function * transition is measured plus or minus 200 mv from steady state. t rsqx t srst t stc t wvkh t rsqz* t rhwx a0 a11 twe dirtyout tclr valid t shrs t rsmv
MPC2105A ? mpc2106a ? mpc2105b ? mpc2106b 17 motorola fast sram ordering information (order by full part number) mpc 210xx xx xx motorola memory prefix part number full part numbers e MPC2105Asg66 mpc2106asg66 mpc2105bsg66 mpc2106bsg66 speed (66 = 66 mhz) package (sg = gold pad simm) MPC2105A = 512kb, synchronous, series resistors mpc2106a = 1mb, synchronous, series resistors mpc2105b = 512kb, synchronous mpc2106b = 1mb, synchronous
MPC2105A ? mpc2106a ? mpc2105b ? mpc2106b 18 motorola fast sram 178 lead card edge MPC2105A/b case 1132a01 package dimensions c l d a a1 2x d2 2x c m 0.006 b l a d3 b m 0.006 c l a r d6 view a a notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in inches. 3. card thickness applies across tabs and includes plating and/or metallization. 4. dimensions e and a5 define a doublesided module. 5. dimension e1 defines optional singlesided module. 6. straightness callout applies to tab area only. dim min max inches a 1.190 1.210 a1 0.545 a2 0.095 a3 0.010 a4 0.195 a5 0.195 b 0.039 0.043 d 5.055 5.065 d1 0.100 d2 0.190 d3 1.255 1.265 d4 3.405 3.410 d5 1.250 bsc d6 0.072 0.076 d7 0.075 0.081 e 0.050 bsc e1 0.075 bsc e 0.210 e1 0.140 e2 0.055 0.070 d4 d5 r d7 view a front view b d1 2x b l 0.006 c l a 4x view a c l a2 a3 a4 b 178x 86x e e1 1 47 48 124254748 89 component area component area 90 178 back view c a5 note 4 e1 note 5 m 0.016 e2 notes 3 and 6 side view e
MPC2105A ? mpc2106a ? mpc2105b ? mpc2106b 19 motorola fast sram 178 lead card edge mpc2106a/b case 113201 c l d a a1 2x d2 2x c m 0.006 b l a d3 b m 0.006 c l a r d6 view a a notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in inches. 3. card thickness applies across tabs and includes plating and/or metallization. 4. dimensions e and a5 define a doublesided module. 5. dimension e1 defines optional singlesided module. 6. straightness callout applies to tab area only. dim min max inches a 1.390 1.410 a1 0.545 a2 0.095 a3 0.010 a4 0.195 a5 0.195 b 0.039 0.043 d 5.055 5.065 d1 0.100 d2 0.190 d3 1.255 1.265 d4 3.405 3.410 d5 1.250 bsc d6 0.072 0.076 d7 0.075 0.081 e 0.050 bsc e1 0.075 bsc e 0.210 e1 0.140 e2 0.055 0.070 d4 d5 r d7 view a front view b d1 2x b l 0.006 c l a 4x view a c l a2 a3 a4 b 178x 86x e e1 1 47 48 124254748 89 component area component area 90 178 back view c a5 note 4 e1 note 5 m 0.016 e2 notes 3 and 6 side view e
MPC2105A ? mpc2106a ? mpc2105b ? mpc2106b 20 motorola fast sram motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, 6f seibubutsuryucenter, p.o. box 5405, denver, colorado, 80217. 3036752140 or 18004412447 3142 tatsumi kotoku, tokyo 135, japan. 81335218315 mfax ? : rmfax0@email.sps.mot.com e touchtone 6 022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://designnet.com 51 ting kok r oad, tai po, n.t., hong kong. 85226629298 MPC2105A/d ?

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